1. Field of the Invention
The field of the invention relates to semiconductor devices and in particular to inverting semiconductor devices made from partially depleted silicon on insulator (SOI).
2. Description of the Prior Art
Cell libraries are known in which cells that fit onto a standard grid are designed for performing particular logical functions. Circuits can then be designed using these standard cells.
When selecting a cell to use, such things as propagation time, required drive strength and capacitance are considered. Propagation time of a signal through a device depends on a sum of the rise time and fall time of that signal. The rise and fall time for a device may be different and depends on the ratio of the width of the NMOS and PMOS transistors forming the device. The width of a transistor is the width of its active region (Wp for the PMOS transistor 10 and Wn for the NMOS transistor 20 in FIG. 1). These widths can be varied to provide either an average delay time that is a minimum of the sum of the rise and fall time or a balanced delay time, in which the rise time equals the fall time. Standard cells may be made available that provide either a lowest average delay time or a balanced delay time.
In standard cells made using bulk processes the initial or DC state of the device prior to it switching will not affect the delay times. However, in devices formed using other processes such as, partially depleted silicon on insulator techniques the propagation delay for rise and fall time may depend on the state of the device when it is inactive prior to it switching. This is because unlike bulk devices where the well of the device is tied to a set voltage, in SOI devices, for example, the “well” of the device is isolated and has a floating potential.
FIG. 1 shows an inverter in transistor and layout form. When a 0 is received at the input the output outputs a 1, and thus, in a transistor formed using partially depleted SOI techniques the “well” of transistor 10 (in this embodiment a PMOS device) is floating between a 1 at the output and a 1 at the high power rail and is thus, at about 1. The “well” of transistor 20 (in this embodiment an NMOS device), however lies between the output 1 and 0, and in this case floats at about 0.3. When a 1 is received at the input there is a 0 at the output and the “well” of transistor 10 floats between 1 and 0 at the output and lies at about 0.7 (1-0.3), while the well of transistor 20 lies between two 0s and therefore floats at about 0. Thus, in the DC or inactive state when the devices are not switching they are not symmetrical and this affects their rise and fall times when they start to switch.
FIG. 2 shows a diagram illustrating different rise and fall times of these devices with DC0 indicating the device having a 0 at its input in the inactive or DC state and DC1 indicating the device having a 1 at its input in the inactive or DC state. Looking at FIG. 2 it becomes clear that setting a ratio of transistors to produce a balanced rise and fall delay propagation time following an inactive state is no longer straightforward as these delays depend on initial state.
However, if these propagation delays are not balanced then problems can result. The difference in propagation delays is termed the history effect and it results in a stretching of a portion of the switching signal when it passes through two inverters and results in the signal no longer being symmetrical. In the SOI partially depleted technology the history effect due to the change in behaviour of the transistors depending on previous switches is particularly marked. Many devices are made from inverting devices arranged in series, and thus, this problem is widespread.
FIG. 3 shows the stretching effect on a symmetric input signal propagated by two inverters formed from partially depleted SOI processes following an inactive state. As there are two inverters arranged in series, they each necessarily have different inputs in all states including an inactive state. Thus, following an inactive state they will have different rise and fall propagation times. This generates a stretching effect when stimulating the path with a symmetric signal (i.e. the high state duration equals the low state duration). The amount of this stretching effect can be calculated by analysing the propagation time on each port. Let's consider a chain of 2N inverters stimulated by a signal starting with a low state (DC0). The odd cells start operating with a DC0 state and the even cells with a DC1 state. As a consequence the propagation delay of the first switch through the cell is tfirst=N·(triseDC0+tfallDC1) whereas the second switch is tsecond=N·(tfallDC0+triseDC1). The stretching effect is given by the difference of both propagation delays which is directly linked to the History Effect as triseDC0 is not equal to triseDC1 and tfallDC0 is not equal to tfallDC1. Note that for bulk technologies there is no stretching effect as the rise and fall delays have a unique value but still a stretching effect may be observed due to local variations. For SOI both the history effect and local variations contribute to signal stretching.
The stretching effect has a detrimental effect on the clock tree as the symmetry of the clock signal is not controlled anymore.
As noted above these problems generally do not occur in bulk devices and nor do they occur in SOI partially-depleted devices operating at a steady state. However, in modern low power systems, clock gating occurs periodically and takes the system back to DC states, thus the non-symmetry effects described above become important.